1. Field of the Invention
This invention relates to methods for detecting and classifying defects on a reticle. Certain embodiments relate to methods that include acquiring images of the reticle at different conditions during inspection of the reticle, detecting defects on the reticle using images acquired at one of the conditions, and classifying the defects on the reticle using images acquired at another of the conditions.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
An integrated circuit (IC) design may be developed using methods and systems such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such methods and systems may also be used to generate a circuit pattern database from the IC design. A circuit pattern database includes data representing a plurality of layouts for various layers of the IC. Data in the circuit pattern database may be used to determine layouts for a plurality of reticles. The terms “reticle” and “mask” are used interchangeably herein.
A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Typically, these polygons can be generally defined by their size and placement on the reticle. Different reticles are used to fabricate different layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
Reticles are used to pattern a resist in a lithography process step, then the to patterned resist is used to form features of the IC on the wafer. Therefore, the patterned features that are formed on a reticle and are to be transferred to the wafer reflect the characteristics of the features that are included in the IC design. For example, the features that are formed on the reticle may be based on and are used to form individual components of the ICs such as those described above.
The complexity of the IC design, therefore, has a direct impact on the manufacture and inspection of reticles. In particular, as the complexity of the IC design increases, successful reticle manufacture becomes more difficult. For instance, as the dimensions of the IC features and the spacings between the features decrease, the dimensions and spacings of features on the reticle also decrease. In this manner, it becomes more difficult to form these features on a reticle due to, for example, limitations of the reticle manufacturing process. In a similar manner, it becomes more difficult to inspect these features due to limitations of the reticle inspection processes. Furthermore, as is known in the art, the difficulty of successfully reproducing these features on wafers increases as the dimensions and spacings decrease.
In addition, as the dimensions of IC features approach the wavelength of the energy source used to print the reticle pattern on wafers, reticle enhancement techniques (RET) such as optical proximity correction (OPC) features are increasingly relied upon to improve transfer of the reticle features to the wafer. In particular, RET features cause the pattern printed on wafers to differ significantly from the pattern physically formed on a reticle. Additional examples of reticle enhancing techniques include, but are not limited to, phase shifting regions, polarization reticles, multiple exposures, off-axis illumination, illumination shapes, and dipole illumination.
OPC features generally take the form of sub-resolution assist features (SRAF) that are formed on the reticle but which do not print on the wafer. Instead, OPC features are designed to increase or decrease the amount of light incident on the wafer proximate certain portions of the features such as corners. OPC features further complicate the design, manufacture, and inspection of reticles. However, due to the assistance that these features provide for printing features with acceptable characteristics, almost all reticles today include OPC features or another type of RET features. Furthermore, optical effects such as mask error enhancement factor (MEEF) may cause additional distortion of the final image at the wafer level. MEEF may be generally defined as the ratio of the critical dimension (CD) of a feature printed in a resist to the CD of a structure formed on a reticle.
Despite the increasing difficulty of reticle inspection, due to the important role that reticles play in semiconductor fabrication, ensuring that the reticles have been manufactured satisfactorily (such that the reticles can be used to produce the desired images on wafers) is critical to successful semiconductor fabrication. In general, during a reticle inspection process, an optical image of the reticle is typically compared to a baseline image. The baseline image is either generated from the circuit pattern data or from an adjacent die on the reticle itself. Either way, the optical image features are analyzed and compared with corresponding features of the baseline image. Each feature difference is then compared against a single threshold value. If the optical image feature varies from the baseline feature by more than the predetermined threshold, a defect may be defined.
In order for inspection to provide useful results, the inspection process is preferably able to not only detect many different kinds of defects but also to discriminate between real defects on the reticle and noise or nuisance events. Noise may be defined as events detected on a reticle by an inspection tool that are not actually defects but appear as potential defects due to marginalities in the inspection tool such as marginalities in data processing and/or data acquisition. Nuisance events are actual defects but are not relevant to the user for the purposes of controlling the process or predicting yield. Moreover, the same defect may be considered a nuisance event at one point in time, but it may later be found to be a relevant defect. In some instances, the number of noise and nuisance events detected by an inspection tool can be reduced by using optimized data acquisition parameters and optimized data processing parameters. In addition, the number of noise and nuisance events can be reduced by applying various filtering techniques to the inspection results. Therefore, one challenge of reticle inspection is to differentiate between real defects and noise or nuisance events such that the results accurately reflect the actual defects without being overwhelmed by noise and nuisance events.
Furthermore, as the dimensions of ICs decrease and the patterns being transferred from the reticle to the wafer become more complex, defects in the features formed on the reticle become increasingly important. In particular, if the pattern is not formed accurately on the reticle, such discrepancies increasingly produce defects on the wafer as the dimensions of the pattern decrease and the complexity of the pattern increases. Therefore, significant efforts have been devoted to developing methods and systems that can be used to detect problems in the pattern on the reticle that will cause problems on the wafer. These efforts are relatively complex and difficult due, at least in part, to the fact that not all discrepancies in the pattern formed on the reticle (as compared to the ideal pattern) will cause errors on the wafer that will adversely affect the IC. In other words, an error in the pattern formed on the reticle may not produce defects on the wafer at all or may produce defects on the wafer that will not reduce the performance characteristics of the IC. Therefore, one challenge of many in developing adequate methods and systems for inspecting a reticle is to discriminate between pattern defects that “matter” and those that do not.
Accordingly, it would be advantageous to develop methods for detecting and classifying defects on a reticle, which do not have one or more of the disadvantages described above.